The present invention relates to technology for increasing the speed of operation of a semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal. More particularly, the present invention relates to technology effectively used for a semiconductor integrated circuit device that has storage circuit blocks such as DRAM and logic circuit blocks on one semiconductor integrated circuit chip and is configured so that a data transfer within the chip is performed synchronously with a clock signal.
In a conventional logic LSI (large-scale semiconductor integrated circuit) in which a storage circuit and logic circuits are formed on a one semiconductor chip, generally a data transfer within the chip is often performed synchronously with a clock signal. For such LSI, when data is transferred from one function circuit to another, inputted data is properly processed before being stored in an internal storage circuit, or data read from the storage circuit is properly processed before being outputted to the outside of the chip, a circuit to receive the data is configured to latch the data synchronously with the rising edge or falling edge of a clock signal (hereinafter referred to simply as a clock). For this reason, it has been common that time required for a data transfer is an integral multiple of the cycle of the clock.
Data propagation delay time occurring during use of circuits such as function circuits may, in some cases, be shorter than one cycle of clock, or in other cases, be a little longer than one cycle of clock, depending on the characteristics of circuits concerned, or the distance of data transfer. Even in such cases, in conventional semiconductor integrated circuit devices, data receive has been performed by latching data on the rising edge or falling edge of a clock whose phase matches that of an internal clock. As a result, time required for data transfer or data transmission is an integer multiple of one cycle of clock, and data has been transferred about one cycle later than actual delay.
If all internal timing signals are adjusted at an optimum timing according to data transfer delay within the chip, the timing of output signals may not match the phase of clock. If such signals are outputted to the outside of the chip, other LSIs that receive the signals and operate synchronously with an external clock could not correctly get the signals. Accordingly, semiconductor integrated circuit devices operating synchronously with a clock must synchronize with the clock at an input end and output end of signal.
Moreover, in the design and development of LSI for which high speed operation is demanded, the LSI is designed so that the margins of setup time and hold time for a clock are minimized to increase its operation speed. However, if the margins are thus minimized, a slight timing lag occurs in an internal clock due to change of element characteristics and parasitic capacity caused by variations in processes, and the slight timing lag of the internal clock may cause circuits to malfunction. In such a case, the manufacturing yield of a semiconductor integrated circuit decreases or its design must be changed. Accordingly, it is desirable that the LSI chip is internally provided with a mechanism by which clock timing can be adjusted at a final stage of process.
As a prior art related to the present invention, according to the invention disclosed in Japanese Published Unexamined Patent Application No. Hei 6(1994)-52676, in a semiconductor integrated circuit device including a storage circuit, optimum setup time and write pulse width are adjusted using a fuse circuit to speed up processing. However, the prior invention, which relates to technology for adjusting signal timing within RAM used as a storage circuit, makes no disclosure of adjusting transmission timing of signals between the RAM and logic circuits comprised of gate arrays and the like on the periphery of the RAM by changing a clock delay. In the prior patent application, although a fuse circuit is used to adjust timing, no disclosure is made of a method of forming the fuse.
An object of the present invention is to reduce total signal propagation delay time from signal input to output and speed up processing in a semiconductor integrated circuit device that includes circuit blocks such as storage circuits and operates synchronously with an external clock.
Another object of the present invention is to provide a semiconductor integrated circuit device that becomes fewer in the number of design changes and the number of mask modifications, is greatly reduced in development period, and is increased in yield.
Another object of the present invention is to provide a semiconductor integrated circuit device which allows timing to be adjusted without using much time for process changes and clock timing adjustment, and causes no increase in costs.
The above described objects and other objects, and novel characteristics of the present invention will become apparent from the description of this specification and the accompanying drawings.
Of inventions disclosed in the present patent application, typical ones are outlined below.
In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks (131, 141, 132, and 142) that receive input signals in response to a first timing signal (xcfx861) based on a clock signal (CLK), and a second circuit block (110) that forms output signals in response to a second timing signal (xcfx862) based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.
According to the above described means, in any portion of the second circuit block in which signal transmission time is not an integral multiple of the cycle of clock, operation is performed based on a timing signal generated to conform to the signal transmission time, whereby total delay time from signal input to output can be reduced and the speed of operation can be increased.
Preferably, time from the acceptance of an input signal in the first circuit blocks to the output of a signal formed in the second circuit block is set to an integral multiple of the cycle of the clock signal. In other words, in a semiconductor integrated circuit device which has a signal input point, a signal output point, and plural circuit blocks provided in series between the signal input point and the signal output point and in which the timings of a signal input operation from the signal input point, a signal output operation at the signal output point, and a signal transmission operation among the plural circuit blocks are respectively controlled by timing signals, when the clock signal cycle is T1, the total of signal response periods of individual circuit blocks of the plural circuit blocks is T2, and the ratio T2/T1 between T1 and T2 is n+xcex1 (n is an integer and xcex1 is a positive number equal to or less than 1), a signal response period from the signal input point to the signal output point is set to n+1 times the clock signal cycle T1. This facilitates synchronization with other semiconductor integrated circuit devices to receive output signals from a semiconductor integrated circuit device to which the present invention is applied, and facilitates the design of a board system and the like.
Moreover, preferably, a timing signal forming circuit is provided which forms the first timing signal and the second timing signal, based on the clock signal, and the timing signal forming circuit has a program element and includes a delay circuit for adjusting the time difference between the first timing signal and the second timing signal by the program element. Thereby, even after the semiconductor integrated circuit device has been manufactured, internal timings can be adjusted, a large margin can be provided for the signal transmission system, and product yield can be increased. The above described program element, which can be formed in various forms, is preferably comprised of fuse devices in terms of circuit occupation area.
In the case where at least one of the above described circuit blocks has a circuit operation setting element and the setting of its circuit operations is changeable depending on the circuit operation setting element, the program element in the delay circuit and the circuit operation setting element in the first circuit blocks are configured with devices having the same configuration as each other. Thereby, a semiconductor integrated circuit device can be obtained which includes a delay circuit capable of adjusting timing without any change of processes.
In the case where the second circuit block is comprised of a random access memory having a defect relieving circuit, the program element in the delay circuit and a setting element for holding defect relief information in the defect relieving circuit in the second circuit block are configured with devices having the same configuration as each other. Thereby, in a semiconductor integrated circuit device including a memory having a redundant circuit, a delay circuit capable of adjusting internal timing can be mounted on an identical chip without any change of processes.
The program element in the delay circuit and the setting element for holding defect relief information in the defect relieving circuit in the second circuit block are provided adjacently to each other. Thereby, program processing such as disconnection by laser irradiation or the like can be performed easily and quickly.
In this case, the program element in the delay circuit and the setting element for holding defect relief information in the defect relieving circuit are nearly linearly juxtaposed. Thereby, program processing can be performed more efficiently.
According to the present invention, in a semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the plural circuit blocks include a first circuit block and a second circuit block that receive input signals in response to a first timing signal based on the clock signal, and a third circuit block that forms output signals in response to a second timing signal based on the clock signal; in a signal transmission system, the third circuit block is provided between the first circuit block and the second circuit block; and a time difference between the first timing signal and the second timing signal is set to a period of a non-integral multiple of the cycle of the clock signal.
According to the above described means, in any portion of the third circuit block in which signal transmission time is not an integral multiple of the cycle of clock, operation is performed based on a timing signal generated to conform to the signal transmission time, whereby total delay time from signal input to output can be reduced and the speed of operation can be increased. Moreover, signals can be outputted synchronously with the clock signal from the second block, facilitating synchronization with other semiconductor integrated circuit devices to receive output signals from a semiconductor integrated circuit device to which the present invention is applied, and easing the design of a board system and the like.
The third circuit block includes a local timing signal generating circuit that generates a third timing signal within the block, based on the second timing signal, and a time difference between the second timing signal and the third timing signal may be a non-integral multiple of the cycle of the clock signal. Since the constraint that a time difference is an integral multiple of the cycle of clock signal is eliminated, operation is performed according to timing reflecting actual delay time, whereby signals can be transmitted at high speed.
The local timing signal forming circuit has a program element and includes a delay circuit for adjusting the time difference between the second timing signal and the third timing signal by the program element. Thereby, even after the semiconductor integrated circuit device has been manufactured, internal timings can be adjusted, a large margin can be provided for a signal transmission system, and product yield can be increased.
The first circuit block and the second circuit block each include a latch circuit that gets input signals to the respective circuit blocks, based on the first timing signal, and the third circuit block includes a latch circuit that gets input signals to the third circuit block, based on the second timing signal. By providing a latch circuit at an input side of each circuit block, synchronization can be established in the signal transmission system by a simple circuit.
In the signal transmission system consisting of the first circuit block, the third circuit block, and the second circuit block coupled in series for signal transmission, one or two or more fourth circuit blocks may be provided in parallel with the third circuit block. Thereby, system functions within the chip can be made advanced, and even if such advanced functions have been achieved, total delay time from signal input to output can be reduced and the speed of operation can be increased.
In the case where the third circuit block and the fourth circuit block have the same circuit configuration, a signal selecting means for selectively transmitting one of output signals corresponding to the circuit blocks is provided in the second circuit block. Thereby, a semiconductor integrated circuit device can be easily achieved in which plural memory circuits such as RAM are mounted.
In the case where a timing signal forming circuit is which forms the first timing signal and the second timing signal, based on the clock signal, the timing signal forming circuit has a program element and includes a delay circuit for adjusting the time difference between the first timing signal and the second timing signal by the program element. Thereby, even after the semiconductor integrated circuit device has been manufactured, internal timings can be adjusted, a large margin can be provided for the signal transmission system, and product yield can be increased.
There are further provided two external terminals through which the clock signal is inputted, and a clock buffer circuit which receives a differential clock signal inputted to the two external terminals and generates a single-phase clock signal. Thereby, timing can be decided at cross points of positive-phase signal and negative-phase signal of differential clock signals, so that clock skew can be minimized and a highly reliable semiconductor integrated circuit device can be obtained.